SAMA5D31 AHB Bus Matrix + LCD

у кого что глючит и не глючит

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Зарегистрирован: 23 май 2017, 17:42
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I had a strange behaviour with the Display (parallel, 800x600) and clock frequency 33 MHZ on SAMA5D31 based board. When the system is loaded with raw NAND (ubifs) and USB (vfat) traffic, strange artifacts are visible on the display. Flickering occured, and picture became unstable. It appears every 5 sec. (aprox).
When, however, the clock frequency is decreased to 26.4 MHz, everything is fine. In the datasheet for the display, 40 MHz is the typical value!
When I on the other hand, increase the display clock frequency to 44 Mhz, it leads to display crash (flickerning and then black out after few secs) without any traffic on NAND either USB.
I came to idea to setup priorities on SAMA5D31 Bus Matrix. There, I found some inconsinstencies in the SAMA5D3 Series DATASHEET.
My questions:
1. Bus Matrix Master Configuration Registers (MATRIX_MCFG0...MATRIX_MCFG15) starting at 0xFFFFEC00 have reset value 0x4 according to the manual. In bootloader I see 0x0, except for the MATRIX_MCFG0 where is 0x1. These registers are not setup in the SPL (or Bootstrap). So, whom do I trust?
2. In the Bus Matrix Priority Registers A or B For Slaves, staring at 0xFFFFEC80, there is a field (1 bit) LQOSENx: Latency Quality of Service Enable for Master x. It is not posible to change this value! It is always 0x0. Did I overlook something? WPEN bit is cleared in the Write Protection Mode Register!
3. In the same register (Bus Matrix Priority Registers A or B) there is a two bit field MxPR: Master x Priority. In the manual is written that values in the Bus Matrix Priority Registers are product dependent. What I see, that these values are 0x3 for intersecting fields master/slave, and zeroes where there is no junction master/slave. Is there some document that covers SAMA5D3 Bus matrix thematics with more reliable details?
Please Help.
Thanks !
I didn't find the right solution from the internet.

- ... matrix-lcd
- Small Business Video Examples

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